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1 ? ha-5002 110mhz, high slew ra te, high output current buffer the ha-5002 is a monolithic, wideband, high slew rate, high output current, buffer amplifier. utilizing the advantages of the intersil d.i. technologies, the ha-5002 current buffer offers 1300v/ s slew rate with 110mhz of bandwidth. the 200ma output current capability is enhanced by a 3 ? output impedance. the monolithic ha-5002 will replace the hybrid lh0002 with corresponding performance increases. these characteristics range from the 3000k ? input impedance to the increased output voltage swing. monolithic design technologies have allowed a more precise buffer to be developed with more than an order of magnitude smaller gain error. the ha-5002 will provide many present hybrid users with a higher degree of reliability and at the same time increase overall circuit performance. for the military grade product, refer to the ha-5002/883 datasheet. features ? voltage gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.995 high input impedance . . . . . . . . . . . . . . . . . . . . . .3000k ? low output impedance . . . . . . . . . . . . . . . . . . . . . . . . 3 ? very high slew rate . . . . . . . . . . . . . . . . . . . . . 1300v/ s very wide bandwidth . . . . . . . . . . . . . . . . . . . . . . 110mhz high output current . . . . . . . . . . . . . . . . . . . . . . . . . . 200ma pulsed output current . . . . . . . . . . . . . . . . . . . . . . 400ma monolithic construction pb-free plus anneal available (rohs compliant) applications line driver data acquistion 110mhz buffer radara cable driver high power current booster high power current source sample and holds video products ordering information part number part marking temp. range (c) package pkg. dwg. # ha2-5002-2 ha2-5002-2 -55 to 125 8 pin metal can t8.c ha2-5002-5 ha2-5002-5 0 to 75 8 pin metal can t8.c ha3-5002-5 ha3-5002-5 0 to 75 8 ld pdip e8.3 ha3-5002-5z (note) ha3-5002-5z 0 to 75 8 ld pdip* (pb-free) e8.3 ha4p5002-5 ha4p5002-5 0 to 75 20 ld plcc n20.35 HA4P5002-5Z (note) HA4P5002-5Z 0 to 75 20 ld plcc (pb-free) n20.35 ha9p5002-5 50025 0 to 75 8 ld soic m8.15 ha9p5002-5z (note) 50025z 0 to 75 8 ld soic (pb-free) m8.15 ha9p5002-9 50029 -40 to 85 8 ld soic m8.15 ha9p5002-9z (note) 50029z -40 to 85 8 ld soic (pb-free) m8.15 *pb-free pdips can be used for through hole wave solder processing only. they are not in tended for use in reflow solder process ing applications. note: intersil pb-free plus anneal products em ploy special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb- free products are msl classified at pb-free peak reflow temperatures that meet or exceed t he pb-free requirements of ipc/jedec j std-020. march 8, 2006 fn2921.11 data sheet caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003-2006. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 fn2921.11 march 8, 2006 pinouts ha-5002 (pdip, soic) top view ha-5002 (plcc) top view ha-5002 (metal can) top view note: case voltage = floating 1 2 3 4 8 7 6 5 out v 2 + nc v 1 - v 1 + v 2 - nc in 19 3 2 20 1 15 16 17 18 14 9 10 11 12 13 4 5 6 7 8 v 2 - nc nc nc nc nc in nc v 1 - nc v 2 + nc nc nc nc nc v 1 + nc out nc in v 2 - v 2 + out v 1 + nc v 1 - nc 2 4 6 1 3 7 5 8 ha-5002
3 fn2921.11 march 8, 2006 absolute maximum ratings thermal information voltage between v+ and v- terminals. . . . . . . . . . . . . . . . . . . . 44v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v 1 + to v 1 - output current (continuous) . . . . . . . . . . . . . . . . . . . . . . . . 200ma output current (50ms on, 1s off) . . . . . . . . . . . . . . . . . . . . 400ma operating conditions temperature range ha-5002-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to 125c ha-5002-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to 75c ha-5002-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to 85c thermal resistance (typical, note 2) ja (c/w) jc (c/w) pdip package*. . . . . . . . . . . . . . . . . . . 92 n/a metal can package . . . . . . . . . . . . . . . 155 67 plcc package. . . . . . . . . . . . . . . . . . . 74 n/a soic package . . . . . . . . . . . . . . . . . . . 157 n/a max junction temperature (hermetic packages, note 1) . . . . . . 175c max junction temperature (plastic packages, note 1) . . . . . . . . 150c max storage temperature range . . . . . . . . . . . . . . -65c to 150c max lead temperature (soldering 10s) . . . . . . . . . . . . . . . . 300c (plcc and soic - lead tips only) *pb-free pdips can be used for through hole wave solder processing only. they are not intended for us e in reflow solder processing applications. caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. maximum power dissipation, in cluding load conditions, must be designed to maintain the ma ximum junction temperature below 175 c for the can packages, and below 150c for the plastic packages. 2. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications v supply = 12v to 15v, r s = 50 ? , r l = 1k ?, c l = 10pf, unless otherwise specified parameter test conditions temp (c) ha-5002-2 ha-5002-5, -9 units min typ max min typ max input characteristics offset voltage 25 - 5 20 - 5 20 mv full - 10 30 - 10 30 mv average offset voltage drift full - 30 - - 30 - v/c bias current 25 - 2 7 - 2 7 a full - 3.4 10 - 2.4 10 a input resistance full 1.5 3 - 1.5 3 - m ? input noise voltage 10hz-1mhz 25 - 18 - - 18 - v p-p transfer characteristics voltage gain (v out = 10v) r l = 50 ? 25 - 0.900 - - 0.900 - v/v r l = 100 ? 25 - 0.971 - - 0.971 - v/v r l = 1k ? 25 - 0.995 - - 0.995 - v/v r l = 1k ? full 0.980 - - 0.980 - - v/v -3db bandwidth v in = 1v p-p 25 - 110 - - 110 - mhz ac current gain 25 - 40 - - 40 - a/ma output characteristics output voltage swing r l = 100 ? 25 10 10.7 - 10 11.2 - v r l = 1k ? , v s = 15v full 10 13.5 - 10 13.9 - v r l = 1k ? , v s = 12v full 10 10.5 - 10 10.5 - v output current v in = 10v, r l = 40 ? 25 - 220 - - 220 - ma output resistance full - 3 10 - 3 10 ? harmonic distortion v in = 1v rms , f = 10khz 25 - <0.005 - - <0.005 - % transient response full power bandwidth (note 3) 25 - 20.7 - - 20.7 - mhz rise time 25 - 3.6 - - 3.6 - ns propagation delay 25 - 2 - - 2 - ns overshoot 25 - 30 - - 30 - % slew rate 25 1.0 1.3 - 1.0 1.3 - v/ns settling time to 0.1% 25 - 50 - - 50 - ns ha-5002
4 fn2921.11 march 8, 2006 differential gain r l = 500 ? 25 - 0.06 - - 0.06 - % differential phase r l = 500 ? 25 - 0.22 - - 0.22 - degrees power requirements supply current 25 - 8.3 - - 8.3 - ma full--10--10ma power supply rejection ratio a v = 10v full 54 64 - 54 64 - db note: 3. . electrical specifications v supply = 12v to 15v, r s = 50 ? , r l = 1k ?, c l = 10pf, unless otherwise specified (continued) parameter test conditions temp (c) ha-5002-2 ha-5002-5, -9 units min typ max min typ max fpbw slew rate 2 v p eak --------------------------- ;v p =10v = test circuit and waveforms figure 1. large and sm all signal response small signal waveforms small signal waveforms out in -15v +15v v 2 + r s r l v 1 + v 2 - v 1 - v out v in r s = 50 ? , r l = 100 ? v out v in r s = 50 ? , r l = 1k ? ha-5002
5 fn2921.11 march 8, 2006 schematic diagram application information layout considerations the wide bandwidth of the ha-5002 necessitates that high frequency circuit layout proced ures be followed. failure to follow these guidelines can result in marginal performance. probably the most crucial of the rf/video layout rules is the use of a ground plane. a ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. other considerations are proper power supply bypassing and keeping the input and out put connections as short as possible which minimizes distributed capacitance and reduces board space. power supply decoupling for optimal device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. ceramic capacitors ranging in value from 0.01 to 0.1 f will minimize high frequency variations in supply voltage, while low frequency bypassing requires large signal waveforms large signal waveforms test circuit and waveforms (continued) v out v in r s = 50 ? , r l = 100 ? v out v in r s = 50 ? , r l = 1k ? r 9 r 10 q 25 q 9 q 10 r 5 q 11 q 15 q 23 r 7 q 21 q 22 q 24 q 27 q 26 r 8 q 20 q 18 q 3 r 4 r 1 q 7 q 4 q 8 r 6 r 3 r 12 q 16 q 14 q 13 r 2 r n3 r 11 q 5 q 6 q 12 r n1 q 19 r n2 v 1 - v 2 - out v 2 + v 1 + q 1 q 2 in q 17 ha-5002
6 fn2921.11 march 8, 2006 larger valued capacitors since the impedance of the capacitor is dependent on frequency. it is also recommended that the bypass capacitors be connected close to the ha-5002 (preferably directly to the supply pins). operation at reduced supply levels the ha-5002 can operate at supply voltage levels as low as 5v and lower. output swing is directly affected as well as slight reductions in slew rate and bandwidth. short circuit protection the output current can be limit ed by using the following circuit: capacitive loading the ha-5002 will drive large capacitive loads without oscillation but peak current limits should not be exceeded. following the formula i = cdv/dt implies that the slew rate or the capacitive load must be controlled to keep peak current below the maximum or use the current limiting approach as shown. the ha-5002 can become unstable with small capacitive loads (50pf) if certain precautions are not taken. stability is enhanced by any one of the following: a source resistance in series with the input of 50 ? to 1k ? ; increasing capacitive load to 150pf or greater; decreasing c load to 20pf or less; adding an output resistor of 10 ? to 50 ? ; or adding feedback capacitance of 50pf or greater. adding source resistance generally yields the best results. out in v+ r lim r lim v 1 - v 2 - v 2 + v 1 + v- i outmax = 200ma (continuous) r lim v+ i outmax ------------------------- - v- i outmax ------------------------- - == 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 25 45 65 85 105 125 temperature (c) maximum power dissipation (w) soic pdip plcc quiescent power dissipation at 15v supplies where: t jmax = maximum junction temperature of the device t a = ambient jc = junction to case thermal resistance cs = case to heat sink thermal resistance sa = heat sink to ambient thermal resistance graph is based on: p dmax t jmax t a ? jc cs sa ++ -------------------------------------------- = p dmax t jmax t a ? ja -------------------------------- = figure 2. maximum power dissipation vs temperature can ha-5002
7 fn2921.11 march 8, 2006 typical application figure 3. coaxial cable driver - 50 ? system r l 50 ? rg -58 50 ? r m 50 ? r s v 1 -v 2 - -12v v 1 +v 2 + +12v v in v out v out v in typical performance curves figure 4. gain/phase vs frequency (r l = 1k ? ) figure 5. gain/phase vs frequency (r l = 50 ? ) figure 6. voltage gain vs temperature (r l = 100 ? ) figure 7. voltage gain vs temperature (r l = 1k ? ) 9 6 3 0 -3 -18 phase frequency (mhz) voltage gain (db) v s = 15v, r s = 50 ? gain -6 -9 -12 -15 0 45 90 135 180 phase shift 1 10 100 9 6 3 0 -3 -18 phase 1 10 100 frequency (mhz) voltage gain (db) v s = 15v, r s = 50 ? gain -6 -9 -12 -15 0 45 90 135 180 phase shift temperature (c) 0.994 0.992 0.990 0.988 0.986 0.984 0.982 0.980 0.978 0.976 0.974 0 20406080100120 -20 -40 -60 voltage gain (v/v) v out = -10v to +10v v s = 15v temperature (c) 0.998 0.997 0.996 0.995 0.994 0.993 0.992 0.991 0 20 40 60 80 100 120 -20 -40 -60 voltage gain (v/v) v out = 0 to -10v v out = 0 to +10v v s = 15v ha-5002
8 fn2921.11 march 8, 2006 figure 8. offset voltage vs temperature figure 9. bias current vs temperature figure 10. maximum output voltage vs temperature figure 11. supply current vs temperature figure 12. supply current vs supply voltage figure 13. input/output impedance vs frequency typical performance curves (continued) temperature (c) 0 20 406080100120 -20 -40 -60 offset voltage (mv) 3 2 1 0 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 v s = 15v temperature (c) 0 20 40 60 80 100 120 -20 -40 -60 bias current ( a) 0 1 2 3 4 5 6 7 v s = 15v temperature (c) 020406080100120 -20 -40 -60 output voltage (v) 11 12 13 14 15 +v out v s = 15v, r load = 100 ? -v out temperature (c) 0 20 40 60 80 100 120 -20 -40 -60 supply current (ma) 3 6 8 9 10 7 5 4 v s = 15v, i out = 0ma 0 2 4 6 8 1012 141618 supply current (ma) 10 8 6 4 2 0 supply voltage ( v) -55c 125c, 25c i out = 0ma 100k 10k 1000 100 10 1 z out 100k 1m 10m 100m frequency (hz) z in impedance ( ? ) v s = 15v ha-5002
9 fn2921.11 march 8, 2006 die characteristics substrate potential (powered up): v 1 - transistor count: 27 process: bipolar dielectric isolation figure 14. v out maximum vs v supply figure 15. psrr vs frequency figure 16. slew rate vs supply voltage figure 17. gain error vs input voltage typical performance curves (continued) 15 12 8 5 t a = 25c 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 v out max, v p-p at 100khz t a = -55c t a = 125c, supply voltage ( v) r load = 100 ? 10k 100k 1m 10m frequency (hz) psrr (db) 80 70 60 50 40 30 20 10 0 100m slew rate (v/ s) 1500 1400 1300 1200 1100 1000 900 6 8 10 12 14 16 18 supply voltage ( v) t a = 25c v s = 15v r l = 600 r l = 1k 150 100 50 0 v out - v in (mv) 0246810 input voltage (volts) -10-8-6-4-2 -50 -100 -150 r l = 100 ha-5002
10 fn2921.11 march 8, 2006 metallization mask layout ha-5002 v 1 - in out v 2 + v 1 + (alt) v 1 - (alt) v 2 - v 1 + ha-5002
11 fn2921.11 march 8, 2006 ha-5002 dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo se ries symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do no t include mold flash or protru- sions. mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
12 fn2921.11 march 8, 2006 metal can packages (can) notes: 1. (all leads) ?b applies between l1 and l2. ?b1 applies between l2 and 0.500 from the reference pl ane. diameter is uncontrolled in l1 and beyond 0.500 from the reference plane. 2. measured from maximum diameter of the product. 3. is the basic spacing from the c enterline of the tab to terminal 1 and is the basic spacing of eac h lead or lead position (n -1 places) from , looking at the bottom of the package. 4. n is the maximum number of terminal positions. 5. dimensioning and tolerancing per ansi y14.5m - 1982. 6. controlling dimension: inch. ?b ?d2 ? e k1 k ?b1 base and seating plane f q ?d ?d1 l1 l2 reference plane l a ?b2 ?b1 base metal lead finish section a-a a a n e 1 c l 2 1 t8.c mil-std-1835 macy1-x8 (a1) 8 lead metal can package symbol inches millimeters notes min max min max a 0.165 0.185 4.19 4.70 - ?b 0.016 0.019 0.41 0.48 1 ?b1 0.016 0.021 0.41 0.53 1 ?b2 0.016 0.024 0.41 0.61 - ?d 0.335 0.375 8.51 9.40 - ?d1 0.305 0.335 7.75 8.51 - ?d2 0.110 0.160 2.79 4.06 - e 0.200 bsc 5.08 bsc - e1 0.100 bsc 2.54 bsc - f - 0.040 - 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 l 0.500 0.750 12.70 19.05 1 l1 - 0.050 - 1.27 1 l2 0.250 - 6.35 - 1 q 0.010 0.045 0.25 1.14 - 45 o bsc 45 o bsc 3 45 o bsc 45 o bsc 3 n8 84 rev. 0 5/18/94 ha-5002
13 fn2921.11 march 8, 2006 ha-5002 plastic leaded chip carrier packages (plcc) a1 a seating plane 0.020 (0.51) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l notes: 1. controlling dimension: inch. conv erted millimeter dimensions are not necessarily exact. 2. dimensions and toleranc ing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. -c- n20.35 (jedec ms-018aa issue a) 20 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.385 0.395 9.78 10.03 - d1 0.350 0.356 8.89 9.04 3 d2 0.141 0.169 3.59 4.29 4, 5 e 0.385 0.395 9.78 10.03 - e1 0.350 0.356 8.89 9.04 3 e2 0.141 0.169 3.59 4.29 4, 5 n20 206 rev. 2 11/97
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn2921.11 march 8, 2006 ha-5002 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05

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